1. Field Of The Invention
The present invention relates to timing devices and, more particularly, to an apparatus for generating a plurality of time markers and for selectively routing the time markers to a plurality of output elements.
2. Description Of The Prior Art
Electronic devices, such as integrated circuits, often operate with timing signals having a particular format, such as return-to-zero non-return-to-zero, surround-by-complement, and inverted and/or delayed versions of these formats. When such devices are to be tested by an automatic test system the particular timing signal required by the device under test must be provided by the test system. In some applications, a single, dedicated circuit is constructed for generating the signal format required. However, sometimes it is necessary for the test system to communicate with many different devices, with each different device requiring a distinct timing format. When the number of such devices is large, it is often infeasible to construct a separate clocking source for each device. Furthermore, the timing characteristics of the device under test may change from time to time as improved versions of the device are constructed. Additionally, the timing characteristics of many devices are not known until the device is connected to the test system.
Prior art attempts to provide flexibility in such systems include forming the desired timing signals using programmable circuitry. In this approach, master clock pulses are counted after a trigger pulse, and the system generates a marker pulse for a timing signal formatting circuit after a prescribed number of pulses has been counted. In one such system, termed the counter-per-marker architecture, a counter is preloaded by the trigger pulse with the number of master clock cycles of delay that are desired. The circuit then generates a marker pulse when the counter has counted down to zero. This method has the drawback of requiring one counter circuit for each marker pulse that is desired.
A related prior art method, termed the comparator-per-marker architecture, involves the use of only one counter, which is reset to zero by each trigger pulse. A register and a digital comparator are then connected to the counter output for each marker pulse desired. Each register contains a prescribed pulse count value, and marker pulses are generated as the clock pulse counter counts through the register values. Many comparator/register circuits can be run from one counter circuit, but this method still requires duplication of comparator/register circuitry for each marker to be generated.
Finally, a particular marker pulse may have to be used for formatting more than one timing signal. In known systems, not necessarily in the prior art, such multiple formats must be known in advance, and the circuit must be hard-wired to accommodate them. This reduces the flexibility of the timing signal generator.